1. Field of the Invention
The invention relates in general to an apparatus for testing an integrated circuit (IC) and in particular to an apparatus for testing the ability of an IC to accommodate jittery input signals and for measuring the amount of jitter in its output signals.
2. Description of Related Art
Digital integrated circuits (ICs) communicate through digital data signals, and when a transmitting IC transmits a digital data signal to a receiving IC, it typically synchronizes state changes in the digital data signal to leading (or trailing) edges of a periodic clock signal so that they occur at predictable times. To produce a data sequence represented by successive states of the digital signal, the receiving IC must digitize the data signal with an appropriate sampling phase and frequency. In some communication systems, a transmitter sending a digital data signal to a receiver also sends a clock signal to the receiver for controlling the timing with which the receiver samples the data signal. In other communication systems the receiver may include a clock recovery system for generating the sampling clock signal locally, using a feedback control system to adjust the phase and frequency of the sampling clock signal based on an analysis of data the receiver acquires by observing the data signal.
FIG. 1 depicts the voltage of a typical serial data signal as a function of time. The signal transitions between high and low logic levels VH and VL differ by a nominal peak-to-peak voltage VPP with transitions occurring with a nominal clock period P. While a transmitting IC may synchronize the edges of a data signal to edges of a clock signal having period P, a data signal can often appear somewhat jittery to a receiving IC because the timing with which data signal edges cross a midpoint level midway between VH and VL can vary to some extent relative to timing of clock signal edges, for example, due to noise introduced into the data signal. For example, while edges 10 and 11 cross over the midpoint level at the expected times, noise in edge 12 causes it to cross over the midpoint level too soon. Noise can also cause variation in the signal's amplitude when it is supposed to be at its high and low logic levels as shown, for example, at points 14 and 15 in the waveform of FIG. 1.
Variation in signal edge timing (jitter) can be random or deterministic. Random jitter arises from random noise in the transmitting IC or in the signal path conveying the signal to the receiving IC. In a system where the transmitting IC sends a clock signal to the receiving IC, noise in the clock signal path can also cause the receiving IC to perceive the data signal to be jittery relative to clock signal edges. In a receiving IC employing a clock recovery system to generate a local clock signal, feedback errors or noise in the clock recovery system can cause jitter in the clock signal, thereby causing the data signal to appear jittery relative to clock signal edges. Random jitter renders the timing of each data signal edge somewhat non-deterministic in that is not possible for the receiving IC to predict the amount of timing error in any individual signal edge arising from random noise.
Deterministic jitter arises mainly from inherent characteristics of the transmitting and receiving ICs and the signal path interconnecting them. For example any transmission line will delay signal edges by an amount that is a function of the path's impedance characteristics and the frequency of the signal. When a digital data signal conveys a bit pattern such as {01010101 . . . }, it will act as a relatively higher frequency signal than when it conveys a bit pattern such as {00000111110000011111 . . . }. Thus the amount by which a signal path delays an edge of a digital signal at any given moment depends on the particular data pattern the signal currently conveys. This “pattern-dependant” jitter is deterministic in that timing error in each data signal edge due to pattern-dependant jitter for a given pattern is predictable based on the nature of the pattern and on characteristics of the hardware implementing the signal path. Deterministic jitter that is not pattern-dependant can arise, for example, from periodic noise that is coherent with the clock signal the transmitting IC uses to time edges.
FIG. 2 is a conventional “eye-diagram” generated by a storage oscilloscope repeatedly sweeping a digital signal so that traces of a large number of the signal's data cycles are superimposed on the display. If the signal were not subject to noise or jitter, the signal trace would follow the path indicated by the solid lines of FIG. 2, but due to noise and jitter, the signal trace can move anywhere in the shaded area of FIG. 2.
Since a receiving IC periodically samples a digital signal between transitions to determine the data sequence it represents, it can tolerate some amount of jitter, but when a digital signal is too jittery, the receiving IC not be able to correctly determine each successive state of the digital signal from the samples it acquires because it will sometimes sample the signal to soon or too late. Digital system specifications therefore require that the amount of jitter in a digital signal remain within acceptable limits. One measure of jitter, called “peak-to-peak jitter” corresponds to the width of the shaded area of FIG. 2 at the nominal crossover point 20, representing a difference in relative timing of earliest and latest arriving signal edges. System specifications typically require peak-to-peak jitter to remain within a predetermined limit.
A receiving IC can also tolerate some amount of noise-induced variation in the voltage of its signal logic levels, but when the variation becomes too large, it will not be able to correctly determine the logic level represented by each sample because the signal may sometimes may fail to be on the correct side of the midpoint voltage at the moment the receiver samples it. Digital system specifications therefore require that the amount of voltage variation in a digital signal remain within acceptable limits. For example, some digital system specifications require that the difference between the lowest detected high logic level and the highest detected low logic level (the “vertical eye opening” shown in FIG. 2) to be no smaller than some specified minimum.
A typical IC tester includes a set of tester channels, each connected to a separate pin of an IC device under test (DUT). An IC test is typically organized into a succession of test cycles, and at any time during a test cycle, each tester channel can either send an input signal to a DUT pin or sample a DUT output signal appearing at the pin to determine whether it is of an expected state. Each tester channel includes a memory containing a sequence of data words (vectors), each corresponding to a separate test cycle and indicating what the tester channel is to do during the test cycle and when during the test cycle it is to do it. For example a vector may tell the tester channel to change the state of a DUT input signal at some time during the test cycle, or may tell the tester channel to sample a DUT output signal to determine whether it is of a particular logic level.
To test a DUT's tolerance for a jittery input signal, a channel could be programmed to produce a DUT input signal having a desired jitter pattern. However while a tester channel can accurately adjust timing of DUT input signal edges, in many applications a typical tester channel cannot control the timing of edges of a DUT input signal with sufficient resolution to produce the desired jitter pattern. What is needed is an IC tester channel that can produce a jittery test signal exhibiting a very accurately controlled jitter pattern.